In many data communication applications, Serializer and De-serializer (SerDes) devices facilitate the transmission between two points of parallel data across a serial link. Data at one point is converted from parallel data to serial data and transmitted through a communications channel to the second point where it received and converted from serial data to parallel data.
At high data rates, frequency-dependent signal loss from the communications channel (e.g., the signal path between the two end points of a serial link) as well as signal dispersion and distortion can occur. As such, the communications channel, whether wired, optical, or wireless, acts as a filter and might be modeled in the frequency domain with a transfer function. Correction for frequency dependent losses of the communications channel, and other forms of signal degradation, often requires signal equalization at a receiver of the signal. Equalization through use of one or more equalizers compensates for the signal degradation to improve communication quality.
An eye pattern, also known as an eye diagram (the “eye”), represents a digital data signal from a receiver that is repetitively sampled and applied to the vertical input (axis), while the horizontal input (axis) represents time as a function of the data rate. The eye diagram allows for evaluation of the combined effects of channel noise and inter-symbol interference on the performance of a baseband pulse-transmission system, and the input data eye is the synchronized superposition of all possible realizations of the signal of interest viewed within a particular Unit interval UI (referred to generally as the EYE).
A data slicer (i.e., a Data Latch) in a SerDes device is used for digitizing an analog signal in the serial data receiver. Precision of the latch threshold has substantial impact on performance (e.g., error rate, jitter tolerance) of the SerDes device. A slicers' accuracy depends on tolerances of manufacturing process and cannot be guaranteed without post manufacturing trimming. In order to make the data slicer threshold independent from integrated circuit (IC) manufacturing imperfections, during an initial phase (or occasionally during operation) the latch is usually subject to a trim procedure which varies offset voltage (e.g., a voltage offset ramp) in order to control latch threshold. A number of latch functional features (e.g., hysteresis and metastability) may interact with trim of the latch. When trimmed, each slicer is provided with zero input signal, and the output of it is averaged over a number of samples to reduce influence of noise and other artifacts in slicer functionality. Trim offset to each slicer is varied until its output is averaged to zero (equal number of “1” and “0” at slicer's output over a number of samples). The offset resulting from trim process is constantly applied to each slicer latch in order to ensure intended threshold independent from manufacturing tolerances.
Known approaches to account for this interaction use multiple trim procedure runs in different directions of offset voltage ramp in order to average out the effect of hysteresis and metastability on the final trim offset choice. The known approaches require a long duration of trim procedure due to multiple trim runs, which makes it impossible to trim slicers quickly at power up and, especially, after exiting power down modes of the SerDes device.